RISC-V Single-Cycle Datapath

EECS 31L — Digital Systems Lab v3.2.0 Preview © 2026 m-elfar.com

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Program (inst_mem)

PC Hex (32-bit) Assembly

Register File (initial)

Data Memory (initial)

Supported Instructions

R-type
add rd, rs1, rs2
sub rd, rs1, rs2
or rd, rs1, rs2
and rd, rs1, rs2
I-type
addi rd, rs1, imm
ori rd, rs1, imm
srai rd, rs1, imm
Load / Store
lw rd, imm(rs1)
sw rs2, imm(rs1)
050100150 200250300350 400450500550 600650700750 800850 50100150200 250300350400 450500 PC flip_flop 8-bit Adder PC+4 inst_mem 64×32 reg_file 32×32 imm_gen sign-ext M U X ALU data_mem 128×32 M U X RegWrite ALUSrc MemWrite MemRead Mem2Reg pc_out rs1 rs2 rd rd_data1 rd_data2 A B alu_out addr rd_data wb imm_out PC 4 opcode funct3/7 0x00 0x00000000 x0 x0 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x04
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