EECS 31L | EX-101 | The Numbers

The numbers in Verilog. What do they mean?

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Last modified: 2026-05-28 22:47
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All questions concern Verilog number literals. Unless stated otherwise, treat values as unsigned.
Part 1 — Syntax. A sized literal has the form width'base value. The base specifier is b (binary), o (octal), d (decimal), or h (hex), and is case-insensitive.
Q1: 4'b1101   bit-width =   base =   value =
8'hAF    bit-width =   base =   value =
6'o52    bit-width =   base =   value =
8'd200   bit-width =   base =   value =
Q2: Which of the following are valid Verilog literals? (Select all that apply.)
💡 HintBinary digits: 0–1. Octal digits: 0–7. Hex digits: 0–9, a–f. Base specifier is case-insensitive.
Q3: 4'hA and 4'ha represent the value. (same / different)
Q4: Is the underscore in 4'b1_101 valid? (yes/no)   Decimal value:
💡 HintUnderscores may appear anywhere after the first digit of the value for readability. They have no effect on the stored value.
Part 2 — Truncation. If the value requires more bits than the declared width, Verilog keeps only the rightmost width bits (truncates from the MSB side).
Q5: 3'b1101  stored bits =   decimal =
4'd20   stored bits =   decimal =
3'hB    stored bits =   decimal =
💡 Hint3'b1101: value 1101 is 4 bits, width is 3 — drop the MSB → 101. 4'd20: 20 = 10100 (5 bits), width is 4 — drop the MSB → 0100. 3'hB: B = 1011 (4 bits), width is 3 — drop the MSB → 011.
Part 3 — Signed interpretation. When treated as signed 2's complement, the MSB is the sign bit. A leading 1 means negative.
Q6: 4'b1101  sign =   value =
4'b0110  sign =   value =
8'hC0   sign =   value =
💡 HintMSB=1 → negative. To find magnitude: invert bits, add 1. 4'b1101 → invert: 0010, +1: 0011 = 3 → value = −3. 8'hC0 = 11000000 → invert: 00111111, +1: 01000000 = 64 → value = −64.
Q7: −5 (4-bit): 4'b
−1 (8-bit): 8'b
−8 (4-bit): 4'b
💡 HintMagnitude in binary → invert all bits → add 1. −5: 0101 → 1010 → 1011. −1: 00000001 → 11111110 → 11111111. −8: 0111 → 1000 → 1000.
Part 4 — Unsized literals. A literal with no width specifier (e.g., 13 or 'hA) defaults to 32 bits in Verilog.
Q8: 13     bit-width =   value =
'hFF   bit-width =   value =
'b1010 bit-width =   value =
Part 5 — x and z. Verilog has four logic values: 0, 1, x (unknown), and z (high-impedance). Both can appear in literals.
Q9: In Verilog, x represents:
Q10: In Verilog, z represents:
Q11: In 4'b1x0z: bit[3] =   bit[2] =   bit[1] =   bit[0] =
Q12: In simulation, an undriven wire has value:
💡 HintAn undriven wire is disconnected — high impedance (z). A reg that is never assigned starts as unknown (x).
Q13: In simulation, a reg declared but never assigned has value: