Modules are the basic building blocks in Verilog used to encapsulate functionality.
4'd9 + 4'd3 = 4'b1111 - 4'b0110 = 4'hC / 4'h3 = 4'hF + 4'h2 = 4'b0011 - 4'b0101 = 4'd12 + 4'd6 = 5'd9 == 4'd9 = 4'd9 == 3'd9 = 4'b1100 != 4'b1100 = 4'hB > 4'hA = 4'd5 >= 4'd5 = 4'b0011 < 4'b0010 = 3'b101 && 3'b011 = 3'b101 || 3'b000 = 3'b000 && 3'b111 = !3'b101 = !3'b000 = 3'b101 & 3'b011 = 3'b3'b101 | 3'b011 = 3'b3'b101 ^ 3'b011 = 3'b~3'b101 = 3'b3'b101 3'b011 = 1'b1 3'b101 3'b011 = 3'b001 3'b101 = 3'b010 3'b101 = 1'b0
&4'b1111 = &4'b1101 = |4'b0000 = |4'b0010 = ^4'b1101 = ^4'b1100 = & = 1'b1 (4-bit value)| = 1'b0 (4-bit value)^ = 1'b1 (4-bit value, give one valid answer)
4'b1011 << 1 = 4'b4'b1011 << 2 = 4'b4'b1011 >> 1 = 4'b4'b1011 >> 2 = 4'b4'b1011 <<< 1 = 4'b4'b1011 >>> 1 = 4'b4'b0101 >>> 1 = 4'b4'b0011 << = 4'b11004'b1100 >> = 4'b00114'b0001 << = 4'b1000
{4'b1010, 4'b0101} = 8'b{1'b1, 3'b010} = 4'b{2'b11, 2'b0, 2'b10} = 6'b{4{1'b1}} = 4'b{3{2'b10}} = 6'b{2{3'b101}} = 6'b{ {1'b0}} = 8'b00000000{2'b1, {2'b01}} = 8'b{ { }} = 6'b110110
condition ? val_if_true : val_if_false.1'b1 ? 4'd10 : 4'd5 = 1'b0 ? 4'd10 : 4'd5 = (4'd3 > 4'd2) ? 4'd1 : 4'd0 = (4'd3 == 4'd4) ? 4'd1 : 4'd0 = ( ) ? 4'd7 : 4'd3 = 4'd3 (use a simple comparison)1'b1 ? : 4'd0 = 4'd91'b0 ? 4'd9 : = 4'd4