EECS 31L | EX-103 | Verilog Module Structure

Modules are the basic building blocks in Verilog used to encapsulate functionality.

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Last modified: 2026-05-28 22:37
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All questions concern Verilog module structure, ports, and simple dataflow assignments.

You find the following code in the wild:

module databus_driver( input [31:0] data, input en, clk, output [31:0] out );
    assign out = en ? data : 32'b0;
endmodule

Q1: The first line declares: the module name the input ports the output ports the port widths war bankrupcy

Q2:
Number of input ports =
Number of output ports =

Q3:
Total number of input bits =
Total number of output bits =

💡 Hint

Each port has a width. A port declared without a range is 1 bit wide.

Q4: What is missing from this module?
a body a soul an endmodule nothing

Q5:
What is the width of out when en = 0? bits
What value does it hold? (decimal)

Fill in the blanks to complete the following module definitions.

Q6: A 4-bit adder. Overflow is discarded.

 adder4 (   A, B,   Y );
     Y = A  B;

Q7: A 1-bit AND gate.

 and_gate (  A, B,  Y );
     Y = A  B;

Q8: A 4-bit 2-to-1 multiplexer (i.e., a multiplexer with 2 inputs and 1 output, but each input and the output are 4 bits wide instead of 1 bit).
When sel = 0, output is A; otherwise output is B.

 mux4 (   A, B,  sel,   Y );
     Y = sel ?  :  ;

Q9: A module that outputs the upper and lower halves of an 8-bit input.

 splitter (  hi, lo,   A );
     hi = A;
     lo = A;

💡 Hint

Part-select syntax: A[high:low] extracts bits from high down to low.