EECS 31L | EX-201 | Dataflow Modeling I

Where does the data flow?

Document version: v0.1a
Last modified: 2026-05-28 22:31
Canvas: [ EECS 31L Workspace ]
Consider the following module: 
module mystery(
    input  wire [3:0] A, B,
    input  wire       sel,
    output wire [3:0] Y,
    output wire       Z
);
    assign Y = sel ? A : B;
    assign Z = &A;
endmodule
Q1: For A=4'b1010, B=4'b0101, sel=1:

Y = 4'b   Z = 1'b
Q2: For A=4'b1111, B=4'b0101, sel=0:

Y = 4'b   Z = 1'b
Consider the following module: 
module bitops(
    input  wire [7:0] A,
    output wire [3:0] HI, LO,
    output wire [7:0] SWAP,
    output wire       ODD_PARITY
);
    assign HI         = A[7:4];
    assign LO         = A[3:0];
    assign SWAP       = {A[3:0], A[7:4]};
    assign ODD_PARITY = ^A;
endmodule
Q3: For A=8'b11001010:

HI = 4'b   LO = 4'b   SWAP = 8'b   ODD_PARITY = 1'b
💡 HintCount the number of 1s in A to determine parity.
Fill in the missing operator or operand in each assign statement.
Q4: Output is high only when both A and B are non-zero (1-bit result).

assign Y = A B;
Q5: Output is the bitwise complement of A.

assign Y = A;
Q6: Output is 1 if A equals B, 0 if definitely not, and x if we cannot tell for sure.

assign Y = A B;
💡 HintLogical equality operator '==' returns x (unknown value) if one or more bits are x. If there are one or more x bits, but the known bits are not equal, then it returns 0 because regardless of the unknown bits, the result is definitely not equal.
Q7: Output is A sign-extended from 4 bits to 8 bits.

assign Y = {{4{}}}, A};
💡 HintSign extension replicates the MSB to fill the upper bits.
Q8: Complete the module. Output Y is 1 when A is greater than B, 0 otherwise.

comparator( input wire [3:0] A, B, output wire Y );
    assign Y = A B;
Q9: Complete the module. Output Y is the XOR of all bits of A (odd parity).

parity( input wire [7:0] A, output wire Y );
    assign Y = A;