EECS 31L | EX-202 | Dataflow Modeling

You are tasked with designing a module with the following specifications using only dataflow modeling (I wonder why).
Name: i_wonder_why
Ports:
  A: 4-bit data input
  SRC: 2-bit source select
  DST: 2-bit destination select
  EN: 1-bit enable
  Y: 4-bit data output
Functionality:
  If EN=0: All Y bits are 0 regardless of other inputs.
  If EN=1: DST selects which bit of Y to update; SRC selects which bit of A to use. All other bits of Y are 0.
As a result, you propose three different designs to implement the same thing.

Part 1 — Design A: One that uses intermediate wires, reflecting a coding style that emphasizes clarity and modularity.

Q1:

module i_wonder_why_design_a(

  // Explicitly declare port directions and sizes

    A,

    SRC,

    DST,

   EN,

    Y

);

  // Declare internal wires

   SBIT; // Selected bit from A

  // The selected bit is based on SRC signal

  assign SBIT = [];

  // If enabled and output bit is selected, connect with selected bit

  assign Y[] = ( && ( == 2'b)) ?  : 1'b; // Output bit 0

  assign Y[] = ( && ( == 2'b)) ?  : 1'b; // Output bit 1

  assign Y[] = ( && ( == 2'b)) ?  : 1'b; // Output bit 2

  assign Y[] = ( && ( == 2'b)) ?  : 1'b; // Output bit 3

endmodule

Part 2 — Design B: One that uses a single assign statement, reflecting a more compact, low-key flex coding style.

Q2: Complete Design B.

module i_wonder_why_design_b(

  // Declare port directions and sizes

    A,

    SRC,

    DST,

   EN,

    Y

);

  // Single assign: if enabled, shift a 1 to DST and mask with selected bit

  // Masking is done by bitwise ANDing. Mask bits are all 0 except the one we want to keep

  assign Y = () ? (4'b0001  ) & ([] ? 4'b1111 : 4'b0000) : 4'b0000;

endmodule

💡 Hint

Shift a single 1 to position DST to create a mask. Use A[SRC] to decide whether to keep or zero out the masked bit.

Part 3 — Design C: always-style, not exactly a dataflow approach but one can't help it.

Q3: Complete Design C.

module i_wonder_why_design_c(

  // Declare port directions and sizes

    A,

    SRC,

    DST,

   EN,

  // Note: output driven in always block must be reg

     Y

);

  // Always block: sensitive to all inputs

  always @() begin

    // Check enable signal

    if () begin

      // Select destination bit based on DST

      case ()

        2'b00: Y = (A[]) ? 4'b : 4'b0000;

        2'b01: Y = (A[]) ? 4'b : 4'b0000;

        2'b10: Y = (A[]) ? 4'b : 4'b0000;

        2'b11: Y = (A[]) ? 4'b : 4'b0000;

        default: Y = 4'b0000;

      endcase

    end else begin

      // Module disabled

      Y = 4'b;

    end

  end

endmodule

💡 Hint

A signal driven inside an always block must be declared as reg. The sensitivity list * means sensitive to all inputs.

Part 4 — Testbench: Verify your design with a testbench.

Q4: Fill in the signal types, sizes, and port connections.

module i_wonder_why_tb();

    A;

    SRC, DST;

       EN;

    Y_a, Y_b, Y_c;



  i_wonder_why_design_a dut_a (

    .A(),  .SRC(),  .DST(),  .EN(), .Y() );

  i_wonder_why_design_b dut_b (

    .A(), .SRC(), .DST(), .EN(), .Y() );

  i_wonder_why_design_c dut_c (

    .A(), .SRC(), .DST(), .EN(), .Y() );



  initial begin

    A = 4'b1010; SRC = 2'b01; DST = 2'b10; EN = 0; #10;

    A = 4'b1010; SRC = 2'b01; DST = 2'b10; EN = 1; #10;

    A = 4'b1010; SRC = 2'b00; DST = 2'b00; EN = 1; #10;

    A = 4'b1010; SRC = 2'b11; DST = 2'b11; EN = 1; #10;

    $finish;

  end

endmodule

Q5: Fill in the expected outputs for each test case.
A=4'b1010; SRC=2'b01; DST=2'b10; EN=0; → Y_a=4'b Y_b=4'b Y_c=4'b
A=4'b1010; SRC=2'b01; DST=2'b10; EN=1; → Y_a=4'b Y_b=4'b Y_c=4'b
A=4'b1010; SRC=2'b00; DST=2'b00; EN=1; → Y_a=4'b Y_b=4'b Y_c=4'b
A=4'b1010; SRC=2'b11; DST=2'b11; EN=1; → Y_a=4'b Y_b=4'b Y_c=4'b

💡 Hint

Trace each test case: find A[SRC], then place it at Y[DST]. If EN=0, all outputs are 0.