EECS 31L EX-601 Arithmetic Logic Unit (ALU)

Part A: Behavioral Modeling

Someone wrote the following code claiming that it is the next generation of 16-bit adders where we just don’t care about carry bits anymore.

module adder_16bit (
  input [15:0] A,  input [15:0] B,  output [15:0] Y
  );
   assign Y = A + B;
endmodule

Q1. Rewrite the above module using behavioral modeling.

module adder_16bit (
  __________ , __________ ,  __________
  );
   __________________________________________________________
endmodule

Q2. True or False: The original module models a combinational circuit, and the behavioral version can still model a combinational circuit.

Q3. True or False: The bit width of the output Y is 16 or 17, depending on the actual values of A and B.

Q4. Suppose that the instructor has asked to use your code to instantiate an adder in his own ALU module. but he can’t make up his mind about the bit width of the adder ports. Now it is 16 bits. Tomorrow it is 32 bits. Rewrite the module header so that the instructor can set the number of bits N to whatever value he wants when instantiating adder_Nbit. Rename the module to adder_Nbit, obviously.

module _______________________________________________________ ;
  assign Y = A + B;
endmodule

Part B: The ALU and You

Q5. True or False: In a typical combinational ALU, the logic circuit for each operation continuously computes its result regardless of the ALU control signal values.

Q6. True or False: In a typical combinational ALU, some operations may have a different number of operands than others.

Q7. True or False: In a typical combinational ALU, a decoder selects the output of exactly one operation to be the ALU output.

Q8. True or False: An ALU with 5-bit opcode can still support 6 operations.

Q9. True or False: In a typical combinational ALU, its output may depend on both the value of its input operands and the value of the opcode.

Part C: ALU Design

Alleged ALU design

Based on the above design, answer the following questions:

Q10. Write down the opcode values in binary for each of the 5 operations.

- Opcode for ADD: __________
- Opcode for SUB: __________
- Opcode for MUL: __________
- Opcode for DIV: __________
- Opcode for PAR: __________

Q11. Using behavioral modeling, write a Verilog module for the ALU shown above. The following are the specifications:

• Module name: alu
• Input and output operands are N-bit wide (parametrized)
• Default value of N is 16
• Use case statements
• Use Opcode values based on the provided design (Q10)
• Operations (see figure):
  • Addition
  • Subtraction (A - B)
  • Multiplication
  • Division (A / B)
  • Parity (1 if the total number of 1’s in A and B is odd, 0 otherwise)
  • Unrecognized opcode: output 0
• Flags:
  • Zero flag Z (1 if the ALU output is 0, 0 otherwise)
  • Negative flag N: 1 if the MSB of Y is 1, 0 otherwise

module __________ #(___________________________) (
  _____________________________ A,
  _____________________________ B,
  _____________________________ Op,
  _____________________________ Y,
  _____________________________ Z,
  _____________________________ N
);

  _____________ @(____________)
  begin
    case (____________________)
      ____________ : _____________________________________________
      ____________ : _____________________________________________
      ____________ : _____________________________________________
      ____________ : _____________________________________________
      ____________ : _____________________________________________
           default : _____________________________________________
    endcase
  end

  // Assign flag values
  _____________________________________________
  _____________________________________________

endmodule