EECS 31L | EX-801 | Processor Design

Document version: v0.4a
Last modified: 2026-06-02 14:48
Canvas: [ EECS 31L Workspace ]
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Part A: Decoding Instructions

You are given a 32-bit RISC-V system. In the microarchitecture, a 32×32 register file is used. All registers are initialized to 0x00000000.
Q1: Decode and execute the following RISC-V instruction: 0x00100133

Step 1: Convert each hexadecimal digit to 4-bit binary. You must write all 4 digits for each hex (e.g., write 0000 instead of 0).
0x00100133 =   

Step 2: Identify the Opcode, funct3, and funct7 fields.
Opcode:
funct3:
funct7:

Step 3: Determine the instruction type (R, I, S, B, U, or J) based on the Opcode.
Instruction Type:

Step 4: Identify the specific instruction. Write only the instruction name without operands (e.g., lb, addi, and).
Instruction Name:

Step 5: Identify the source(s) and destination register. Write register names as x0–x31. Write none if there is no second source.
Source 1:   
Source 2:   
Destination:

Step 6: Write the final value written back to the destination register in hexadecimal (e.g., 0x00000000).
Final Value:
💡 HintFor RISC-V R-type instructions, opcode is bits [6:0], rd is [11:7], funct3 is [14:12], rs1 is [19:15], rs2 is [24:20], funct7 is [31:25]. Opcode 0110011 with funct3=000 and funct7=0000000 encodes ADD.
The register file currently holds the following values: 
Register| Reg. | Register    
Address | Name | Value       
--------|------|-------------
   0x00 | x0   | 0x0000_0000 
   0x01 | x1   | 0x0000_A3F2 
   0x02 | x2   | 0x0000_4567 
   0x03 | x3   | 0x0000_1BE4 
   0x04 | x4   | 0x0000_7C09 
   0x05 | x5   | 0x0000_D451 
   0x06 | x6   | 0x0000_0E8B 
   0x07 | x7   | 0x0000_6F3A 
   0x08 | x8   | 0x0000_0004 
   0x09 | x9   | 0x0000_0FFF 
   else | ...  | 0x0000_0000
Q2: Decode and execute the following RISC-V instruction: 0x4081_54B3
Write register names as x0–x31. Write none if there is no second source.

0x4081_54B3 = (binary)
Opcode: --- funct3: --- funct7:
Instruction Type:
Instruction Name (aka mnemonic):
Source 1:   
Source 2:   
Destination:
Final Value of destination register:
💡 HintFor RISC-V R-type instructions, opcode is bits [6:0], rd is [11:7], funct3 is [14:12], rs1 is [19:15], rs2 is [24:20], funct7 is [31:25]. You can find the instruction name by
1. Looking up the opcode first to find the instruction type,
2. Then looking up funct3 within that instruction type, and if necessary,
3. Looking up funct7 if there are multiple instructions with the same opcode and funct3.
Q3: Decode and execute the following RISC-V instruction: 0x00F4_3693
Use register values stated in Q2.
If funct7 is not used, write none.
For sources:
- Write x0–x31 for registers
- Write imm if source 2 is an immediate
- Write none if source 2 is not used.
Unless specified otherwise, all values are in hexadecimal (e.g., write 0x1 or 0x00001 etc.).

0x00F4_3693 = (binary)
Opcode: --- funct3: --- funct7:
Instruction Type:
Instruction Name (aka mnemonic):
Source 1:      stored value:
Source 2:      stored value:
Destination:
Final Value of destination register:
💡 HintFor RISC-V I-type instructions, opcode is bits [6:0], rd is [11:7], funct3 is [14:12], rs1 is [19:15], imm[11:0] is [31:20]. There is no funct7 — I-type instructions are identified by opcode and funct3 alone. SLTIU sets rd to 1 if rs1 is less than the sign-extended immediate, treating the comparison as unsigned.