EECS 31L | EX-901 | Debugging and Synthesis

Q1: Snippet 1
Characterize the block.

always @(*) begin
    if (sel)
        y = a;
    else
        y = b;
end

Synthesizable Infers combinational logic Infers latch Infers flip-flop Incomplete assignment Clocked block Uses blocking assignment Uses nonblocking assignment

💡 Hint

Trace every branch and ask: is y assigned in all cases?

If y is assigned on every path → infers combinational logic
If any path leaves y unassigned → incomplete assignment → infers latch

Then check the assignment operator: = is blocking, <= is nonblocking.

Q2: y: type reg wire always driven may hold state

💡 Hint

Ask: where is y assigned, and is it assigned on every path?

If assigned inside a procedural block → must be declared reg
If assigned on every execution path → always driven
If any path leaves it unassigned → may hold state

Q3: Snippet 2
Characterize the block.

always @(*) begin
    if (en)
        y = d;
end

Synthesizable Infers combinational logic Infers latch Infers flip-flop Incomplete assignment Clocked block Uses blocking assignment Uses nonblocking assignment

💡 Hint

Trace every possible value of en and ask: is y assigned in all cases?

If y is assigned on every path → infers combinational logic
If any path leaves y unassigned → incomplete assignment → infers latch
A latch is valid synthesizable hardware

Q4: y: type reg wire always driven may hold state

💡 Hint

Trace every possible value of en and ask: is y assigned on every path?

If assigned inside a procedural block → must be declared reg
If assigned on every path → always driven
If any path leaves it unassigned → may hold state

Q5: Snippet 3
Characterize the block.

always @(posedge clk) begin
    if (rst)
        q <= 0;
    else
        q <= d;
end

Synthesizable Infers combinational logic Infers latch Infers flip-flop Incomplete assignment Clocked block Uses blocking assignment Uses nonblocking assignment

💡 Hint

Look at the sensitivity list, then trace every branch.

If sensitivity list contains posedge/negedge → clocked block → infers flip-flop, not latch
If q is assigned on every path → no incomplete assignment

Then check the assignment operator: = is blocking, <= is nonblocking.

Q6: q: type reg wire always driven may hold state

💡 Hint

Ask: is q assigned on every triggering event, and what happens between events?

If assigned inside a procedural block → must be declared reg
If assigned on every triggering event → always driven
If it retains its value between triggering events → may hold state

Q7: Snippet 4
Characterize the block.

always @(posedge clk or posedge rst) begin
    if (rst)
        q <= 0;
    else
        q <= d;
end

Synthesizable Infers combinational logic Infers latch Infers flip-flop Incomplete assignment Clocked block Uses blocking assignment Uses nonblocking assignment

💡 Hint

Compare the sensitivity list to Snippet 3 and trace every branch.

If sensitivity list contains posedge/negedge → clocked block → infers flip-flop
If q is assigned on every path → no incomplete assignment

Q8: q: type reg wire always driven may hold state

💡 Hint

Ask: is q assigned on every triggering event, and what happens between events?

If assigned inside a procedural block → must be declared reg
If assigned on every triggering event → always driven
If it retains its value between triggering events → may hold state

Q9: Snippet 5
Characterize the block.

always @(*) begin
    case (op)
        2'b00: y = a + b;
        2'b01: y = a - b;
        2'b10: y = a & b;
    endcase
end

Synthesizable Infers combinational logic Infers latch Infers flip-flop Incomplete assignment Clocked block Uses blocking assignment Uses nonblocking assignment

💡 Hint

op is 2 bits wide — list all possible values and check whether each has a matching case arm.

If all values are covered or a default exists → infers combinational logic
If any value is unhandled → incomplete assignment → infers latch

Q10: y: type reg wire always driven may hold state

💡 Hint

Check whether y is assigned for every possible value of op.

If assigned inside a procedural block → must be declared reg
If assigned for every value → always driven
If any value leaves y unassigned → may hold state

Q11: Snippet 6
Characterize the block.

always @(*) begin
    #10;
    y = a | b;
end

Synthesizable Infers combinational logic Infers latch Infers flip-flop Incomplete assignment Clocked block Uses blocking assignment Unsynthesizable construct

💡 Hint

Identify every construct in the block and ask whether it has a hardware equivalent.

If all constructs map to hardware → synthesizable
If any construct is simulation-only → unsynthesizable construct → not synthesizable

Then check whether y is assigned on every path.

Q12: y: type reg wire always driven may hold state

💡 Hint

Trace every execution path and ask: is y assigned on all of them?

If assigned inside a procedural block → must be declared reg
If assigned on every path → always driven
If any path leaves it unassigned → may hold state

Q13: Snippet 7
Characterize the block.

initial begin
    y = 0;
end

Synthesizable RTL Combinational block Infers latch Infers flip-flop Incomplete assignment Clocked block Uses blocking assignment Unsynthesizable construct

💡 Hint

Ask: does this block react to input changes, or does it run exactly once at the start of simulation?

If the block runs once at time 0 and never again → it is an initial block, not a combinational or sequential block
initial blocks have no hardware equivalent → unsynthesizable construct

Then check the assignment operator.

Q14: y: type reg wire

💡 Hint

Any signal assigned inside a procedural block must be declared reg.
Do not apply fully assigned or may hold state — those characterize reactive logic. This block runs once at time 0; the signal is a simulation variable, not synthesized storage.

Q15: Snippet 8
Characterize the block.

assign y = a & b;

Synthesizable RTL Combinational block Infers latch Infers flip-flop Incomplete assignment Clocked block Uses blocking assignment Unsynthesizable construct

💡 Hint

assign is a continuous assignment — it is not a procedural block.

The output updates immediately whenever any input changes → combinational
There is no clock and no missing path → no latch, no flip-flop
Continuous assignments are synthesizable RTL

Q16: y: type reg wire fully assigned may hold state

💡 Hint

The target of a continuous assign statement must be declared wire, not reg.
y is always driven because the continuous assignment is always active.

Q17: Snippet 9
Characterize the block.

assign y = a & b;
assign y = a | b;

Synthesizable RTL Combinational block Infers latch Infers flip-flop Multiple drivers Clocked block Uses blocking assignment Unsynthesizable construct

💡 Hint

Count how many sources drive y.

If more than one assign drives the same signal → multiple drivers
Multiple drivers on the same net is illegal in Verilog → not synthesizable

Q18: y: type reg wire

💡 Hint

The target of a continuous assign must be declared wire.
Do not apply fully assigned or may hold state — the design is invalid due to multiple drivers.

Q19: Snippet 10
Characterize the block.

and_gate u0 (
    .a(x),
    .b(y),
    .out(z)
);

Synthesizable RTL Combinational block Infers latch Infers flip-flop Multiple drivers Clocked block Uses blocking assignment Unsynthesizable construct

💡 Hint

Module instantiation is structural RTL — it wires submodule ports to signals in the parent module.

No always block, no assign → none of the block characterizations apply
Structural instantiation is synthesizable

Q20: z: type reg wire fully assigned may hold state

💡 Hint

Signals connected to submodule output ports must be declared wire in the parent module.
z is driven by the submodule output, so it is fully assigned as long as the submodule is active.

Q21: Snippet 11
Characterize the block.

initial begin
    clk = 0;
    forever #5 clk = ~clk;
end

Synthesizable RTL Combinational block Infers latch Infers flip-flop Multiple drivers Clocked block Uses blocking assignment Unsynthesizable construct

💡 Hint

Identify every construct and ask whether each has a hardware equivalent.

initial blocks run once at simulation start → unsynthesizable
forever loops have no hardware equivalent → unsynthesizable
#5 timing delays have no hardware equivalent → unsynthesizable

Q22: clk: type reg wire

💡 Hint

Any signal assigned inside a procedural block must be declared reg.
Do not apply fully assigned or may hold state — clk is a simulation-only variable driven by a forever loop with no synthesizable meaning.