EECS 31L • Study Notes • Motivation
Mahmoud Elfar • Spring 2026 • v0.1
v0.1: Initial version
Table of Contents
TBD
0. Motivation
I have decided to write these notes for two reasons:
On one hand, the textbook is easy to follow but has too many “discrepancies” to my liking, and
on the other hand, the IEEE 1800-2017 standard is very comprehensive (it is the definitive reference for Verilog) but can be difficult to navigate for beginners.
Unfortunately, my attention span is non-existent, so my notes will look like lists within lists.
Our goal for this course is for you to be able to describe (model), design, test, analyze, and (hopefully) synthesize digital systems using Verilog.
Verilog is a hardware description language (HDL) that allows you to model digital systems through describing things about them (dataflow, behavior, structure).
You should know:
There are two mainstream HDLs: Verilog and VHDL.
Verilog: relatively easier to learn, more relaxed syntax and typing
VHDL: more strict syntax and typing, more verbose, and so not the best choice for beginners
We achieve those goals through the following objectives:
Learn the language basics, which involves:
Its syntax — what can you write without the simulator cursing back at you
Its semantics — understanding the meaning behind what you write
Its constructs — learning the common ways the language is used to do its job (in modeling digital systems)
Learn the three levels of abstraction by which we can describe a digital system:
By describing how the data flows through the system from inputs to outputs
By describing how the system should behave based on inputs (present) and states (past)
By describing how the system is structurally built from smaller, interconnected components
Learn how to test and analyze our designs using simulation, which involves:
Understanding how simulation works (simulation semantics, event scheduling, etc.)
Learning how to write (virtual) testbenches to poke and prod our design to verify it works as intended
Learning how to read and interpret simulation waveforms (timing diagrams drawn by the simulator) along with techniques for debugging and troubleshooting
Learn how to synthesize our designs (translate them to actual hardware), which involves:
Understanding the synthesis process and how it works
Learning what constructs are synthesizable and which are not
Learning what an FPGA is and ho to program one with our designs without setting the world on fire
2. The Picture Behind the Picture
There is a hidden agenda for EECS 31L that instructors choose to keep to themselves (for a good reason). The most important goal of this course is non of the above — those are just means to an end. The end here is:
To get very, very familiar with microarchitectures, which are the building blocks of all computing systems in existence.
The complexity of computing systems is surreal once you start to peel the layers of abstraction. HDL allows us to focus on just the right level of abstraction to both understand the inner workings of microarchitectures and to design one ourselves without needing a lifetime to do so.