EECS 31L: Digital Systems Lab

Course Description

It’s lab time.

Study Notes

00. Motivation to Verilog and EECS 31L
01. Verilog Basics
02. Dataflow Modeling
03. Behavioral Modeling
04. Delay Control
05. Structural Modeling
06. Processor Design
07. Instruction Set Architecture
08. Microarchitecture
09. Synthesis

Resources

Datapath-v2 Simulator — A web-based RISC-V datapath simulator. Use it to test your understanding of ISA encoding and decoding.

Exercises (manual and autograded)

Exercise 101 Numbers
Exercise 102 Operators
Exercise 103 Modules
Exercise 201 Dataflow Modeling
Exercise 202 Dataflow Modeling
Exercise 601 Arithmetic Logic Unit (ALU) solution
Exercise 801 Processor Design I
Exercise 802 Processor Design II
Exercise 901 Synthesis

Office Hours

Drop in any time during these hours — no reservation needed. Select an event to see who and where. None works for you? Send an email with a subject line that starts with "[31L]".